Embedded dynamic random access memories (eDRAM) are widely used for their improved performances in high-speed applications, such as computing units (CPU).
In eDRAM circuits, local bit lines are connected to eDRAM cells and global bit lines, which are further connected to control circuits. Through the global bit lines and the connecting local bit lines, write operations may be performed to write to the eDRAM cells. The local bit lines typically include two lines with often-inversed phases, namely BL and BLB. The global bit lines also include two lines with often-inversed phases, namely GBL and GBLB.
Conventionally, before a write operation of an eDRAM cell, equalization is performed to short the local bit lines BL and BLB. After the equalization and local bit lines BL and BLB pre-charge are finished, and the write select enable signal WSSL is turned on, the values pre-charged on the global bit lines GBL and GBLB are written to the local bit lines BL and BLB. The word line connected to the eDRAM cell is then turned on to write the values on the local bit lines into the capacitor in the eDRAM cell.
FIG. 1 illustrates waveforms obtained from a conventional eDRAM circuit, wherein a “1” is to be written into an eDRAM cell storing a “0.” Line 20 indicates the voltage on the word line connected to the eDRAM cell. The falling edge 22 indicates turning on the word line. Line 24 is the voltage on a write select enable line, which voltage controls writing the local bit lines BL and BLB from global bit lines GBL and GBLB. The rising edge 26 of line 24 indicates turning on the writing. Lines 28 and 30 represent voltages on local bit lines BL and BLB, respectfully. It is noted after the rising edge 26 of line 24 occurs, bit line voltage 28 turns downward first before it flips and rises (refer to the voltage inside dotted circle 32). Extra time is thus needed for this flip action. This is partially because the writing of values from global bit lines to local bit lines occurs after turning on the sense amplifier (at time t′). At this time, the voltage on bit line BL is still lower than the voltage on bit line BLB. The voltages on the bit lines BL and BLB are thus amplified in the wrong direction first, before they are amplified in the right direction, which bit line BL has a higher voltage than bit line BLB. Actually, during this period, the voltage stored in the memory cell drops before it rises.
The extra voltage flip results in two adverse effects. First, the time needed for local bit lines BL and BLB to be fully charged is lengthened. This adversely affects the speed for write operations. As matter of fact, write operations typically take more recovery time (write recovery) than read operations (read recovery), and thus are the bottlenecks of eDRAM memories. Second, the local bit lines BL and BLB, without enough time and/or margin to be fully charged, will cause the reduction in the voltages written into the memory cells. It is often found that the initial voltages in eDRAM memory cells are lower than after read operations, which cause the rewriting of the memory cells. New methods are thus needed to solve the above-discussed problems.